RE: [vhdl-200x-ft] Question On Type Genericity

Thanks for your explanation.

I still have some questions:

1) In the revised version of my example, you enter as generic a function succ, do I need to write this function or can I pass the attribute 'succ at
instantition time :

entity counter is
   generic ( type count_type; low, high : count_type;
                 function succ ( V : count_type ) return count_type );

2 ) How would you rewrite the following code :

entity add_substract is
   generic ( type signal_type, type enum_operation_type);
   port ( clk : in bit; operation : in enum_operation_type; data1_in : in
signal_type ; data2_in : in signal_type ; data_out : out signal_type );
end entity add_substract;

-- signal_type can be integer,signed, unsigned ....
-- enum_operation_type is a enum (add,sub,maxval,minval)

architecture behavioral of add_substract is
begin
   add_substract_behavior : process is
      variable count : count_type := low;
   begin
      wait until clk = '1';
      if operation=add then
           data_out <= data1_in +data2_in;
      elsif operation=sub then
          data_out <= data1_in - data2_in;
     elsif operation = maxval then
         if data1_in > data2_in then
              data_out <= data1_in;
         else
              data_out <= data2_in;
         end if;
     else -- operation = minval
         if data1_in < data2_in then
              data_out <= data1_in;
         else
              data_out <= data2_in;
         end if;
      end if;
   end process add_substract_behavior;
end architecture behavioral;

3) Will those 2 examples be only accepted by simulators or the intention
is also to have them supported by synthesis tools?

Kind Regards,
Yannick
 
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Yannick Grugni Design Competence Center
Leuven
VLSI Engineer Interleuvenlaan 74-82
Tel: +(32)16.390.742 3001 Leuven
yannick.grugni@philips.com Belgium
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Received on Wed Jan 19 02:33:01 2005