RE: [vhdl-200x-ft] Question On Type Genericity

Yannick,
 
The intention is for formal types to be allowed in any place where you can
have a generic list. So that includes entities, components and blocks as
well as packages and subprograms.
 
Regarding your example: The entity declaration is fine, but the process in
the architecture has a problem. Since the formal type could be associated
with any actual type, there is no guarantee that the actual will eb a
discrete type. So it would not be legal to use the 'low, 'high and 'succ
attributes.
 
An earlier version of the type-generics proposal was based more closely on
Ada's type generics, and would have allowed you to specify that the formal
type be a discrete type. However, in the interest of keeping the current
proposal for VHDL simple and compatible with future extensions for
object-oriented types, no type classing is provided for formal type
generics.
 
You could, however, revise your example as follows:
 
entity counter is
   generic ( type count_type; low, high : count_type;
                 function succ ( V : count_type ) return count_type );
   port ( clk : in bit; data : out count_type );
end entity counter;

architecture behavioral of counter is
begin
   count_behavior : process is
      variable count : count_type := low;
   begin
      data <= count;
      wait until clk = '1';
      if count = high then
         count := succ(count);
      else
         count := low;
      end if;
   end process count_behavior;
end architecture behavioral;

You could then instantiate the entity as follows:
 
c : entity work.counter(behavioral)
        generic map ( T, T'low, T'high, T'succ )
        port map ( ... );
 
I'm assuming here that, since the 'succ attribute is a function, it can be
associated as an actual with the formal subprogram generic. This is
something not explicitly mentioned in the current proposal, but seems to
make sense.
 
Cheers,
 
PA
 

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
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-----Original Message-----
From: owner-vhdl-200x-ft@eda.org [mailto:owner-vhdl-200x-ft@eda.org] On
Behalf Of yannick.grugni@philips.com
Sent: Wednesday, 19 January 2005 01:40
To: vhdl-200x-ft@eda.org
Subject: [vhdl-200x-ft] Question On Type Genericity
I am new so I don't know if it's the good place to ask the question. 
I have seen that there is a proposal to allow formal types in a generic
interface clause. 
Is it only intended to be use for packages and subprograms or can I use it
also for entities? 
Can someone tell me if the code below will be accepted? 
entity counter is 
   generic ( type count_type); 
   port ( clk : in bit; data : out count_type ); 
end entity counter; 
architecture behavioral of counter is 
begin 
   count_behavior : process is 
      variable count : count_type := count_type'low; 
   begin 
      data <= count; 
      wait until clk = '1'; 
      if count = count_type'high then 
         count := count_type'succ(count); 
      else 
         count := count_type'low; 
      end if; 
   end process count_behavior; 
end architecture behavioral; 
Kind Regards,
Yannick
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Yannick Grugni                              Design Competence Center Leuven
VLSI Engineer                                       Interleuvenlaan 74-82
Tel: +(32)16.390.742                            3001 Leuven
yannick.grugni@philips.com           Belgium
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