[vhdl-200x-ft] Question on Type and Package Generics

Peter,
I have a question on instantiating packages.
If I create a generic package as follows:
package MuxPkg is
   generic( type array_type) ;

   function Mux4 (
     Sel : array_type(1 downto 0) ;
     A : array_type ;
     B : array_type ;
     C : array_type ;
     D : array_type
   ) return array_type ;
end MuxPkg ;
package body MuxPkg is

   function Mux4 (
     Sel : array_type(1 downto 0) ;
     A : array_type ;
     B : array_type ;
     C : array_type ;
     D : array_type
   ) return array_type is
   begin
     case Sel is
       when "00" => return A ;
       when "01" => return B ;
       when "10" => return C ;
       when "11" => return D ;
       when others => return (A'Range => A(A'left)'left) ;
     end case ;
   end function Mux4 ;
end MuxPkg ;

To create an implementation for types std_logic_vector and
unsigned I do the following:

Library ieee ;
     Use ieee.std_logic_1164.all ;
     Use ieee.numeric_std.all ;
Package MuxPkg_slv is new work.MuxPkg
     Generic map (array_type => std_logic_vector) ;

Library ieee ;
     Use ieee.std_logic_1164.all ;
     Use ieee.numeric_std.all ;
Package MuxPkg_unsigned is new work.MuxPkg
     Generic map (array_type => unsigned) ;

Finally the question:
When I instantiate a package,
1) do I need to reference the library and use clauses
    prior to each instantiated package since I am creating
    a primary unit and the context clause is consumed by the
    primary unit,
    -- or --
2) do I need only one reference to the library and use clauses
    prior to the first package instantiation sufficient -
    similar to instantiating components in an architecture
    -- or --
3) I don't need any package references before the generic
    package and package references are only required to be
    referenced at the point of usage.

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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