RE: [vhdl-200x-ft] FT27: optional architectures

Selon Peter Ashenden <peter@ashenden.com.au>:

> Tristan,
>
> > * One problem with optionnal architecture is that when an
> > architecture is obsoleted, you don't really know wether you
> > should elaborate without architecture or fail to elaborate.
> > The same problem already exists with the package body.
>
> You use the reserved word "open" to indicate that no architecture be
> included. Thus, if an architecture is obsoleted, you replace all references
> to it in binding indications with "open".
Ok, I was not clear enough.
Suppose you are using default bindings and default configurations.
Suppose the only architecture of an entity (which is instantiated) is
obsoleted.
How your design will elaborate: fails or without architecture for the
instantiated entity.

> > * The second problem is how do you configure the entity ?
> > Since the entity can have component instantiation, you should
> > be able to configure them.
>
> The current situation is this: A block configuration that occurs
> immediately within a configuration declaration or immediately within a
> component configuration configures the equivalent block corresponding to the
> design entity. If the block configuration names an architecture, it
> configures the design entity comprising the entity and the architecture.
>
> What's new in the proposal is that, if the block configuration uses the
> reserved word "open" instead of an architecture name, the design entity
> consists of the entity declaration alone. The block configuration contains
> configuration items for the contents of the entity declaration. That may
> include component instances and nested blocks.
We don't understand each other.
What's new too is that, an entity may contain component instantiation.
Currently, there is no way to configure them (of course).
Furthermore, the label of a component instantiation (C.I.) in an entity can
be the same as a label of a C.I. in an architecture.
How do you address this issue ?

> > * Finally, as a proposal too, we should be able to configure
> > the architecture of a design entity instantiation.
> > Currently, it is not possible to do that.
>
> I'm sorry, I don't understand what it is that you're suggesting. Would you
> care to elaborate?
Sure.
With VHDL 93, you can instantiate entities directly:
 C: entity Work.X (Y) port map (P1 => S1, P2 => S2);
However, you can omit the architecture name:
 C: entity Work.X port map (P1 => S1, P2 => S2);
But you can't configure which architecture you want to use. I'd like to be
able to configure them.

Tristan.
Received on Tue Dec 21 01:41:37 2004