Re: [vhdl-200x-ft] Implicitly referencing std.textio and library IEEE

Selon VhdlCohen@aol.com:

> Unless the packages conflict with each other, I am in favor of integrating
> the packages as part of VHDL, and eliminate the need to separately identify
> which package I need.
> This is done in Verilog and SystemVerilog. SV has integrated new system
> functions and methods, but they are all part of the language. You don't
> import packages that are part of the language!
> In my mind, a package is a library, which is only make accessible when used.
> I still remember the posting in comp.lang.vhdl where a user felt relief when
> switching to VG because he longer had to type the "library IEEE; use
> IEEE.std_1164.all".
> From my perpective, why force the user to get down to those levels of details
> when the types and methods described in those packages are standards.
> Ben Cohen
I really understand this point of view.
However, this point of view break the VHDL spirit.
VHDL and Verilog are two opposites way to handle features:

Verilog:
* a bag of anything (unless I am wrong); no real structure.

VHDL:
* a core: 1076
* additionnal packages: 1164, 1076.x
Each time you want to use an additionnal package, you have to say it explicitly.
VHDL shares this structured way with many many languages: C, C++, java...

Each time a feature has to be added in Verilog, it is added in the core.
Therefore the core is huge and difficult to read.

Currently, with VHDL, just understand the core, and write additionnal features
in VHDL. This can't be done in verilog, since the core is not yet powerful
enough.

Furthermore, not everyone want to use ieee.std_logic_1164. Think about people
who just use bit/bit_vector, or AMS-VHDL.

For your user on comp.lang.vhdl, I have two comments:
* He should use a good editor/IDE, which may automatically add the context
clauses.
* He surely doesn't understand VHDL beyond basic feature, and in this case,
 Verilog may be better for him.

Tristan.
Received on Mon Dec 20 02:39:58 2004