RE: [vhdl-200x-ft] Suggestions re FT18 Boolean equivalence

Steve,

My understanding was that the condition operator would only be *implicitly*
applied in the context of a condition. What I've suggested in item 4 is a
way for the condition operator to be explicitly applied. If the condition
operation is to be defined as an operator, we need to allow for it in the
expression grammar. The FT18 proposal specifies that it be an operator with
lowest precedence, but doesn't say where it fits into the expression
grammar. I've filled in the missing piece of the puzzle.

The alternative is not to treat it as an operator, but as a function. In
that case, we would need to invent a name for it that conforms to the rules
for identifiers, say, to_boolean_condition. Then the function can be
applied just like any other function. The risk is that legacy code might
already define a homograph, etc.

Hope this clarifies my suggestion.

Cheers,

PA

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
Stirling, SA 5152                            Fax: +61 8 8339 2616
Australia                                    Mobile: +61 414 70 9106
> -----Original Message-----
> From: Bailey, Stephen [mailto:SBailey@model.com] 
> Sent: Tuesday, 23 November 2004 02:02
> To: Peter Ashenden; vhdl-200x-ft@eda.org
> Subject: RE: [vhdl-200x-ft] Suggestions re FT18 Boolean equivalence
> 
> 
> I'm OK with everything except for item 4.  Perhaps I missed 
> something in the meetings I haven't been able to attend.  A 
> quick review of FT18 didn't expose anything obvious, but I 
> might have missed it there.
> 
> I thought we had agreed that boolean equivalence (or 
> condition operator) would only be applied in a condition 
> context.  But, item 4 appears to expand on expression.  I'm 
> missing the connection from limited contextual use to a 
> broader use.  I also don't understand:
> 
>    if_expression ::=
>      {logical_expression if condition , } logical_expression 
> 
> Seems like you could write something like:
> 
>   a := ?? B if c = d;
> 
> This appears to be an attempt to combine boolean equivalence 
> (FT18) with polynary expressions (FT10A).
> 
> -Steve Bailey
> 
> > -----Original Message-----
> > From: owner-vhdl-200x-ft@eda.org
> > [mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Peter Ashenden
> > Sent: Sunday, November 21, 2004 6:47 PM
> > To: vhdl-200x-ft@eda.org
> > Subject: [vhdl-200x-ft] Suggestions re FT18 Boolean equivalence
> > 
> > Folks,
> > 
> > I've just been looking over FT18 in preparation for drafting
> > an LCS, and have some suggestions.
> > 
> > 1. I'd suggest using ?? for the unary operator symbol rather
> > than condition?. Currently, all operator symbols are either 
> > strings that don't contain letters, or are reserved words.  
> > Reserved words are identifiers.
> > The string condition? isn't a reserved word, but does 
> contain letters.
> > Using ?? instead will have less impact on lexers and be more 
> > consistent with existing lexical conventions.  It's also more 
> > lexically consistent with ?=.
> > 
> > 2. I'd suggest defining ??[bit return boolean] in STANDARD
> > and ??[std_ulogic return boolean] in STD_LOGIC_1164.  This 
> > would be consistent with our principle of defining operations 
> > on a type in the same package as the type.
> > Legacy models won't be broken, since they won't have 
> > expressions of type bit or std_ulogic as conditions, so the 
> > implicit invocation of ?? won't occur.
> > The only change would be that some previously illegal models 
> > would now be legal (mostly with desired behaviour!).
> > 
> > 3. I'd suggest the ?? operator be referred to as the
> > condition operator, since the term "equivalence" usually 
> > means the same thing as the equals operator for boolean value.
> > 
> > 4. Since the ?? operator is to have lowest precedence, along
> > with if expressions, the grammar can be 
> > 
> >   expression ::=
> >     [ condition_operator ] if_expression
> > 
> >   if_expression ::=
> >     {logical_expression if condition , } logical_expression
> > 
> >   logical_expression ::=
> >       relation { and relation }
> >     | ...
> > 
> > Placing the optional condition operator in the expression
> > grammar like this is analogous to placing the optional sign 
> > in the production for simple_expression.  If you want to 
> > include a use of ?? within an expression, you can always 
> > parenthesize, for example
> > 
> >   b1 /= (?? cs_n)
> > 
> > Comments?
> > 
> > Cheers,
> > 
> > PA
> > 
> > 
> > --
> > Dr. Peter J. Ashenden                        peter@ashenden.com.au
> > Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
> > PO Box 640                                   Ph:  +61 8 8339 7532
> > Stirling, SA 5152                            Fax: +61 8 8339 2616
> > Australia                                    Mobile: +61 414 70 9106
> > 
> > 
> > 
>