[vhdl-200x-ft] proposal submission

IEEE 200X Fast Track Change Proposal

ID: FT-28 (?)

Proposer: Karl Eisenhofer
email: karl@terasystems.com

Status: Open
Proposed: 10/18/2004
Analyzed: Date
Resolved: Date

Enhancement Summary:

        Relex restrictions on unassociated and unconnected subelements of
        ports to allow unassociated and unconnected subelements of
        non-resolved composite types.

Related issues:
Relevant LRM section:

     1.1.1.2

Enhancement Detail:
----------------------------

    Change the final sentance of section 1.1.1.2 from

    "It is an error if some of the subelements of composite formal port are
    connected and others are either unconnected or unassociated."

    To:

    "It is an error if some of the subelements of a resolved composite type
    on a port are connected and other subelements of that type are either
    unconnected or unassociated."

    Note that a std_logic_vector for example is not a resolved composite
type, but
    rather is composite of resolved types.

    Several synthesis tools already permit this kind of specification
and the
    implementation implications of this are well understood. The additional
    analysis complexity associated with this is minimal.

Analysis:
----------------------------
[To be performed by the 200X Fast Track Working Group]

Resolution:
----------------------------
[To be performed by the 200X Fast Track Working Group]
Received on Mon Oct 18 12:01:10 2004