Re: [vhdl-200x-ft] FT10A Syntax Change Proposals

Marcus,
Ternary expressions have highest precendence,
so the following two are equivalent:

    Y <= A if B, C and D;

    Y <= A if B, (C and D) ;

Furthermore if I write,
    Y <= A if ASel, B if BSel, C ;

this would be equivalent to:

   process (A, ASel, B, BSel, C)
   begin
     if ASel then
       Y <= A ;
     elsif BSel then
       Y <= B ;
     else
       Y <= C ;
     end if ;
   end process ;

In some ways with the ',' form this is familar as
it is similar to selected signal assignment.
WRT to readability, anyone can make something more
readable (or less readable). For example,

For simple things, the following may make sense:
     Y <= A when ASel, B when BSel, C when CSel, D when DSel, E ;

For more interesting things, perhaps blank lines are what is needed:
     Y <=
        A1 and A2 when ASel,
        B1 and B2 when BSel,
        C1 and C2 when CSel,
        D1 and D2 when DSel,
        E1 and E2 ;

Maybe others can also speak up as to what they think.

Cheers,
Jim

> Jim Lewis writes:
> > I have received a proposals to change the syntax of FT10A.
>
> Great!
>
> > Alternative 2: Use parens to surround the condition:
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ copy & paste?
> > nnary_expression ::=
> > {logical if condition else } logical
>
> Most nnary (or nested ternary) expressions are painful to read. This
> solution seems to be a reasonable compromise.
>
> BTW: What would be the priority of this kind of operator?
>
> For instance, is
>
> Y <= A if B else C and D;
>
> equivalent to
>
> Y <= A if B else (C and D);
>
> or
>
> Y <= (A if B else C) and D;
>
> ?
>
> Best regards,
> Marcus

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~