Re: [vhdl-200x-ft] comments on ft25

Hi Karl,

The LRM restricts the case statement's expression's type.
 From the LRM section 8.8

"The expression must be of a discrete type, or of a one-dimensional array type whose
element base type is a character type. This type must be determinable independently
of the context in which the expression occurs, but using the fact that the expression
must be of a discrete type or a one-dimensional character array type."

As a result the only allowable type for a & b is std_logic_vector.

Later in the same section the LRM , restrictions are placed on the case expression
when it is a one-dimensional character array type. The result of these restriction
are such that the length of the expression is determinable at compile type.
So expression like ( assuming a and b are std_logic_vectors):

   a, a(1 downto 0) are allowed,
expression like
   a & b, a + b, a AND b are not allowed because the resulting length is
unknown at compile time.

FT25 is to allow the length of the case statement's expression to be determined
at elaboration/run time and that length must match the choice's length.

So the following cases are currently illegal but would be legal with FT25

case ( a & b) is
  when "1110" ...

end

case ( a AND "0010" ) is
   when "1010" =>
  ...
end

case ( a & '0' & b ) is
   when "11111" =>
end

case std_logic_vector'( a(0) & a(1)) is
   when "11" =>
end

The following current are illegal can would continue to be illegal

case ( a & b ) is -- this would produce an elaboration/runtime error that a&b is 4 long and the choice is 8
   when "11111111"
end

case ( a & b ) is -- illegal because the choices have different lengths
  when "111" => ..
  when "11000" =>
end

case ( a(1) & a(0) ) is -- ambiguous because a(1) & a(0) can be either std_logic_vector or std_ulogic_vector
   when "11" =>
...
end

Regards,
   John

Karl Eisenhofer wrote:
> Suppose you declare
>
> variable a, b : std_logic_vector(1 downto 0);
>
> ...
>
> case (a & b) is
>
> how does an analyzer differentiate between a 4 wide std_logic_vector and a
> 2 wide array of 2 wide std_logic_vector? In other words do the when
> expressions look like
>
> when "1000"
>
> -or-
>
> when ("10", "00")
>
> ?
>
> Concats are not deterministic without some contextual type or subtype.
> The case expression does not have any
> such context and thus an analyzer cannot distinguish. Is the suggestion
> that in those cases, a qualified expression IS required?
>
> karl
>

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