Re: [vhdl-200x-ft] Bit Rules & methodology for handling math issu es

From: Jim Lewis <Jim@SynthWorks.com>
Date: Wed Jul 07 2004 - 11:37:14 PDT

Ryan,
> C. Encouraging good DSP design by forcing the designer to specify what
> happens to the bits.
I agree.
OOPS. Let me correct this one,
So the following is good:
    Y_ufixed <= Resize(A_ufixed + B_ufixed, ...) ;

Is it not also a good design practice to encourage
designers to specify when they are mixing operand types?
    Y_sfixed <= Resize(A_sfixed + to_sfixed(B_ufixed)) ;

Cheers,
Jim

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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Received on Wed Jul 7 11:37:16 2004

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