RE: [vhdlsynth] Re: [vhdl-200x-ft] Bit size rules

[from previous posts...]

> > Change the interpretation of ascending ranges to maintain
> > the bit values.
> This one will leave us with an inconsistency to numeric_std

I agree. The discontinuity with the rest of VHDL is surely
unacceptable.

> > The killer feature of a fixed point type is that it gives
> > an unambiguous value to each bit.

Agreed.

May I suggest a different and, I believe, less
disruptive approach?

RATIONALE
~~~~~~~~~
numeric_std follows the rest of VHDL in attaching no special
significance to bit numbers. Instead the leftmost bit of
a vector is taken to be the most significant, and the
rightmost bit implicitly has the weight 2**0. This
behaviour is of course consistent with common usage.

Fixed-point values, by contrast, have no implied
significance for their least significant bit. Fixed-point
objects must have some feature of their representation that
attaches an object- specific binary weight to the least
significant bit. Within VHDL the most obvious, and I
believe the correct, way to represent this is to use
vector subscripts as bit numbers (binary weights). Every
fixed-point proposal I've seen uses some variant on this
theme.

However, in order to preserve sensible copy semantics,
it's essential that the leftmost bit of any numeric
vector be the most significant.

Consequently, fixed-point types should always have
descending ranges.

PROPOSAL
~~~~~~~~
Require that any fixed-point object or subtype have
a descending array range.

IMPLEMENTATION SUGGESTION (1)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Initially the "descending range" constraint can be
enforced informally using assertions in the fixed-
point subprograms.

IMPLEMENTATION SUGGESTION (2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modify the base language so that unconstrained
vector types can be declared to have a range that
is required to be ascending or descending. I don't
wish to propose any specific syntax at this point, but
by way of example you could imagine a construct such
as this:

  type MY_DESCENDING_VECTOR is
      array(integer range <->) of std_logic;

  type MY_ASCENDING_VECTOR is
      array(integer range <+>) of std_logic;

Given these type definitions, it would be an error
(detectable at elaboration time or sometimes earlier)
to declare a named or anonymous subtype with the wrong
range direction.

Since this change would affect only error checking and
not any other part of the language, it seems to me that
it would be fairly straightforward to add and implement.

I have encountered a number of situations where this
change would have been beneficial.

-- 
Jonathan Bromley, Consultant
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