Re: [vhdl-200x-ft] More ideas on 1164 and 1076.3

David,
> In browsing through some code, I have noticed a procedure called
> "to_slv" cropping up all over the place. This appears to really
> be calling "to_stdlogicvector", but people don't want to spell it
> out.
>
> <proposal>
> Add an alias to "std_logic_1164" and "numeric_std" called "to_slv"
> which calls "to_stdLogicVector".
> </proposal>
>
> Any thoughts? to_stdulogicvector? to_bitvector?

To_stdlogicvector set a bad precedent. If we are going
to use long names, we should use the full long name:
to_std_logic_vector and not to_stdlogicvector.

I realize we cannot remove the historical functions, but
if we are going to create to_slv, we should also create
an alias for to_std_logic_vector and any new ones like
to_bit_vector should have the long name.

I have some concerns about to_std_logic_vector being in
numeric_std. It would really depend on the parameters
you are thinking about. Can you provide function
interfaces. I was thinking that things like to_std_logic_vector
with an integer input should go in numeric_std_unsigned.

> Another one is that in the numeric_std package, often you need
> to do operations on both signed and unsigned numbers. The way
> we handle this now with casting is clumsy.
>
> <proposal>
> Add the following functions to numeric_std and numeric_bit:
> function "+"(L : UNSIGNED; R: SIGNED) return SIGNED;
> function "+"(L : SIGNED; R: UNSIGNED) return SIGNED;
. . .
> function "<="(L : UNSIGNED; R: SIGNED) return boolean;
> function "<="(L : SIGNED; R: UNSIGNED) return boolean;
> </proposal>

This would be bad. Currently this is done in std_logic_arith
and causes ambiguity with literals:

    signal A_sv, Y_sv : signed(7 downto 0) ;

    Y_sv <= A_sv + "1111" ; -- is it signed or unsigned.

Cheers,
Jim

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Jim Lewis
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