Folks,
Greg makes a good point - thanks for drawing it to our attention. I did
some quick checking, and found that the boundary scan description language
(BSDL) uses linkage ports for non-functional ports (eg, VDD, VSS, N/C, ...).
A BSDL description of a device is a VHDL entity declaration that lists all
of the pin connections as ports, and associates test information with the
ports using attributes.
If we were to remove linkage ports from VHDL, all of the BSDL descriptions
out there would no longer be valid VHDL. A better approach may be to liaise
with the 1149.1 folks and define linkage ports specifically to mean no
semantics rather than implementation-defined semantics, and to review the
allowed interconnections of linkage ports with ports of other modes.
Cheers,
PA
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106 > -----Original Message----- > From: Gregory D. Peterson [mailto:gdp@utk.edu] > Sent: Tuesday, 1 June 2004 00:17 > To: Bailey, Stephen > Cc: gdp@utk.edu; peter@ashenden.com.au > Subject: Re: [vhdl-200x] RE: [vhdl-200x-ft] Removal of > deprecated features > > > Steve, > > Hope all is going well for you. I've been lurking and > watching much of > the VHDL > revision discussion/debates. I'm glad to see some of the > consolidation > finally happening. > I'm going to be at the DAC for a few days - hopefully I will > see you. I > won't be around > at the end of the week for the DASC meetings though. > > I was just reading some about IEEE 1149 and 1532 a while ago > and it seems to me that some of the code description for > one/both of these standards uses > linkage ports. > If I get the time I will track it down, but I wanted to give > you a heads up > that there might > be some other IEEE standards impacted by deleting linkage > ports. (And for > the record, > I agreed at the time about getting rid of them. We just need > to be careful > not to break > other standards.) > > Greg > > At 10:05 AM 5/31/2004, you wrote: > >I don't know of any reason to keep the features or continue to have > >them > >identified for deprecation. > > > >-Steve Bailey > > > > > -----Original Message----- > > > From: owner-vhdl-200x-ft@eda.org > [mailto:owner-vhdl-200x-ft@eda.org > > > > <mailto:owner-vhdl-200x-ft@eda.org> > > ] On Behalf Of Peter Ashenden > > > Sent: Monday, May 31, 2004 1:59 AM > > > To: vhdl-200x-ft@eda.org > > > Subject: [vhdl-200x-ft] Removal of deprecated features > > > > > > Folks, > > > > > > Clause 13.10 of the VHDL LRM identifies linkage ports and > > > replacement characters as deprecated language features. Is there > > > any objection to removing them from the FT revision? If > not, can we > > > add that as a FT language change? > > > > > > Cheers, > > > > > > PA > > > > > > -- > > > Dr. Peter J. Ashenden peter@ashenden.com.au > > > Ashenden Designs Pty. Ltd. www.ashenden.com.au > > <www.ashenden.com.au> > > > PO Box 640 Ph: +61 8 8339 7532 > > > Stirling, SA 5152 Fax: +61 8 8339 2616 > > > Australia Mobile: +61 > 414 70 9106 > > > > > > > > > >------------ > >Stephen Bailey > >ModelSim Verification TME > >Mentor Graphics > >sbailey@model.com > >303-775-1655 (mobile, preferred) > >720-494-1202 (office) > >www.model.com <www.model.com> > > Dr. Gregory D. Peterson > Assistant Professor > Electrical and Computer Engineering > University of Tennessee > Knoxville, TN 37996-2100 > (865)-974-6352 (voice) > (865)-974-5483 (fax) > gdp@utk.edu >Received on Tue Jun 1 20:01:20 2004
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