[vhdl-200x-ft] FT14 arrays of arrays and slices

With FT14/FT15, we can constrain array ports and signals
using the following syntax:
   type std_logic_matrix is array (natural range<>) of std_logic_vector ;
   subtype Matrix_5x5 is std_logic_matrix(4 downto 0)(4 downto 0) ;
   signal A : std_logic_matrix(7 downto 0)(5 downto 0) ;

Is there anything that can be done to make
indexing of arrays of arrays more consistent with the
above syntax?

   constant Matrix_5x4 : std_logic_matrix (0 to 4) := (
     0 => "0000",
     1 => "0001",
     2 => "0010",
     3 => "0011",
     4 => "0100"
   ) ;

   signal row : std_logic_vector(3 downto 0) := (others => '0') ;
   signal partial_row1 : std_logic_vector(1 downto 0) := (others => '0') ;
   signal partial_row2 : std_logic_vector(1 downto 0) := (others => '0') ;
   signal col : std_logic_vector(0 to 4) := (others => '0') ;
. . .

   row <= Matrix_5x4(4) ; -- "0100"
   partial_row1 <= Matrix_5x4(3)(1 downto 0) ; -- "11"
   partial_row2 <= Matrix_5x4(3)(2 downto 1) ; -- "01"
   -- col <= Matrix_5x4(0 to 4)(3) ; -- "0011" -- not what I want

   I would like Matrix_5x4(0 to 4)(3) = "00000" an array of std_logic.

Is there a practical application of where the current syntax does
something that is useful and in use?

Do we need to consider additional syntax when constraining arrays
of arrays so we can indicate what we are doing?

For example:
   signal A : std_logic_matrix(7 downto 0).(5 downto 0) ;

and:
    col <= Matrix_5x4(0 to 4).(3) ;

For the full example, see the attached code.

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;

entity slicing is
end entity slicing ;
architecture testcase of slicing is

  type std_logic_matrix is array(natural range <>) of std_logic_vector(3 downto 0) ;
  type std_logic_matrix3 is array(natural range <>) of std_logic_matrix(0 to 1) ;

  constant Matrix_5x4 : std_logic_matrix (0 to 4) := (
    0 => "0000",
    1 => "0001",
    2 => "0010",
    3 => "0011",
    4 => "0100"
  ) ;

  signal row : std_logic_vector(3 downto 0) := (others => '0') ;
  signal partial_row : std_logic_vector(1 downto 0) := (others => '0') ;
  signal col : std_logic_vector(0 to 4) := (others => '0') ;
begin
  process
    variable WriteBuf : line ;
  begin
    for i in 0 to 4 loop
      row <= Matrix_5x4(i) ;
      partial_row <= Matrix_5x4(i)(1 downto 0) ;
      wait for 20 ns ;
      row <= Matrix_5x4(i) ;
      partial_row <= Matrix_5x4(i)(2 downto 1) ;
      wait for 20 ns ;
    end loop ;

    for i in 0 to 3 loop
      for j in 0 to 4 loop
        col(j) <= Matrix_5x4(j)(i) ;
      end loop ;
      wait for 20 ns ;
    end loop ;
    
    for i in 0 to 3 loop
-- col <= Matrix_5x4(0 to 4)(i) ;
      write(WriteBuf, Matrix_5x4(0 to 4)(i)) ; -- not what I want
      writeline(Output, WriteBuf) ;
      wait for 20 ns ;
    end loop ;

    report "Done" severity failure ;
  end process ;

end testcase ;

    
Received on Sat May 29 22:58:01 2004