[vhdl-200x-ft] process_ff

In the last meeting, we deferred process_ff because
using the historical methods of creating a FF were
complicated and perhaps out of scope of what we
really want to require simulators to do.

How about requiring rising_edge/falling_edge to be used
when process_ff is used? It would still require
some smart resolution WRT asynchronous events, but it
is much more trackable than my previous proposal.
Note this would also suggest that we implement
rising_edge/falling_edge for bit during fast track.

reg: process_ff
begin
   if rising_edge(clk) then
     AReg <= A ;
   end if ;
end ;

async_reg1: process_ff
begin
   if nReset = '0' then
     AReg <= '0' ;
   elsif rising_edge(clk) then
     AReg <= A ;
   end if ;
end ;

async_reg2: process_ff
begin
   if rising_edge(clk) then
     AReg <= A ;
     BReg <= B ;
   end if ;
   if nReset = '0' then
     AReg <= '0' ; -- A has reset, but not B
   end if ;
end ;

With reset coded as async_reg2, there is no implication
on B during reset.

bad_async_reg3: process_ff
begin
   if nReset = '0' then
     AReg <= '0' ; -- A has reset, but not B
     -- BReg <= BReg ; -- implied since it is not assigned

   elsif rising_edge(clk) then
     AReg <= A ;
     BReg <= B ;
   end if ;

end ;

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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