Subject: [vhdl-200x-ft] Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: VhdlCohen@aol.com
Date: Mon Dec 08 2003 - 17:15:21 PST
In a message dated 12/8/2003 3:05:58 PM Pacific Standard Time,
Jim@synthworks.com writes:
The meeting minutes for the VHDL-200X-FT meeting, San Jose
Dec 4, 2003 are at:
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/ft_mtg_04_dec_03.pdf
Arrays of Unconstrained Arrays
type std_logic_matrix is array of std_logic_vector ;
Ben: This is not consistent with VHDL methods for declaring
unconstrained arrays. Also it prevents user defined indeces.
I recommend the following:
type std_logic_matrix is array (natural range<>) of std_logic_vector;
type std_logic_matrix2 is array (natural range<>, (natural range<>)
of std_logic_vector ;
--------------------------------------------------
Records & Interfaces (after meeting)
Proposal 3: add mode
Mode IfRecType_Mode_Model1 : IfRecType := (
Sig1 => in,
Sig2 => out
end record ;
Mode IfRecType_Mode_Model2 : IfRecType := (
Sig1 => out,
Sig2 => in
end record ;
BEN: I like that style
--------------------------------------------------
Overloading "&" and To_String?
Ben: Great idea!
--------------------------------------------------
-Sequential usage of conditional and Selected Signal Assignment
- Make conditional signal assignment a ternary operator
Ben: YES!
--------------------------------------------------
Add "if else" for conditional signal (deprecate when else?)
AReg <= A if rising_edge(Clk)
Ben: No objections.
--------------------------------------------------
Signal Expressions in Port Maps
Ben: We need that!
--------------------------------------------------
Read Output Ports
Read output ports
Value read will be locally driven value
?Erroneous if additional drivers outside local block?"
Helpful for writing assertions
Ben: The read should return the current value of the local drivers of teh
architecture, and not the resolved value of the signal at the higher level.
Thus if within architecture, S<= '1', and in instantiation S at the port is
driven with '0' (resolved to 'X'), then
a read of the out port from within the architecture should return
the driving value '1'.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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