Subject: Proposals for Stop, Finish and Reset Procedures
From: Bailey, Stephen (SBailey@model.com)
Date: Tue Nov 18 2003 - 19:49:42 PST
> Attached is a proposal I put together that is based on VHPI functionality for adding a standard procedures (presumably in a Utils package in library IEEE) that defines STOP, FINISH and RESET (restart at time 0) procedures that can be called from VHDL code. The first two are equivalent to Verilog's $stop and $finish system tasks.
>
> The functionality falls within the scope of the Environment functional team. However, since it is based entirely on VHPI functionality which will become part of the standard (assuming ballot success) next year, the Fast-Track team could choose to accept this proposal within their scope. As always, comments are appreciated.
> > <<stop_finish.txt>>
> ------------
> Stephen Bailey
> TME, Mentor Graphic's Model Technology Group
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com
>
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