Re: [vhdl-200x-dta] Review of: [vhdl-200x] Revised white paper on type genericity

From: Jim Lewis <Jim@SynthWorks.com>
Date: Fri Apr 23 2004 - 07:12:51 PDT

Peter,
> Regarding the distinction between parameters and ports: I think the
> distinction is useful for the user.
Perhaps I am foolish in this regard, anyone else have an opinion?

> We already have inconsistency between subprogram and
> other items with interface lists. In subprograms, the order of syntactic
> elements is "procedure/function", name, interface list, "is". For
> components and entities, the order is "component/entity", name, "is",
> interface lists.
My current plan as part of MP is to propose to make "is" optional.

Jim

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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Received on Fri Apr 23 07:12:55 2004

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