Re: [vhdl-200x-dta] Review of: [vhdl-200x] Revised white paper on type genericity

Peter,
With respect to the syntax for subprogram generics,
I am concerned that V2 syntax is going in the wrong
direction. While I like consistency with ADA,
I think we have a bigger requirement for consistency
with VHDL.

One of the objectives of VHDL-200X-MP is
to improve the consistency of VHDL syntax. If you
introduce this inconsistency in subprogram generics,
I would need to propose optional syntax for entities
and blocks that makes a flavor that is consistent
with the new subprogram generics. I really don't
want to have to do this.

Port vs. Parameter:
 From a language developer's perspective using parameter
makes sense. From a user's perpsective, we are passing IO to
an object, so using a different keyword is inconsistent. Does
naming parameters and ports differently for the
compiler's/language developer's benefit buy us anything?

If really need to have a different keyword, perhaps in
MP I can make the port and port map keywords optional
for entities?

Cheers,
Jim

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Jim Lewis
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