[vhdl-200x-dta] RE: [vhdl-200x] Revised white paper on type genericity

Peter:

Re 2.1, I dont like the concept of instantiating a generic package as a declarative item.
At beginning of section 2.1, the generic package instantiation is defined to be semantically
equivalent to a normal package (and a design unit). This is good.
In current VHDL, just like
you cannot have a package declaration as a declarative item, I suggest that we not
support a generic package instantiation as a declarative item. We should try
to follow the normal package rules, i.e. inclusion of a package (including a
generic package instantiation) is achieved by using the use clause.

regards,
- bhasker

-----Original Message-----
From: Peter Ashenden [mailto:peter@ashenden.com.au]
Sent: Sunday, April 18, 2004 11:56 PM
To: vhdl-200x-dta@eda.org
Cc: vhdl-200x@eda.org
Subject: [vhdl-200x] Revised white paper on type genericity

Folks,

Attached is a revised version of my earlier white paper proposing exensions
to generics. Changes are:

- simplification of generic types to be incomplete type definitions
- allowing package instances in declarative parts
- change to syntax of generic subprograms
- removal of formal package generics

The idea is that this would be a relatively simple initial extension to VHDL
to allow specification of things like lists, queues and sparse arrays, such
as have been requested for verification and modeling enhancement. The way
in which the extensions have been formulated leaves the way open for further
extensions for object-oriented classes and type reflection.

Steve wanted to discuss this at the telecon later this week.

Cheers,

PA

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
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