Folks,
Attached is a revised version of my earlier white paper proposing exensions
to generics. Changes are:
- simplification of generic types to be incomplete type definitions
- allowing package instances in declarative parts
- change to syntax of generic subprograms
- removal of formal package generics
The idea is that this would be a relatively simple initial extension to VHDL
to allow specification of things like lists, queues and sparse arrays, such
as have been requested for verification and modeling enhancement. The way
in which the extensions have been formulated leaves the way open for further
extensions for object-oriented classes and type reflection.
Steve wanted to discuss this at the telecon later this week.
Cheers,
PA
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106
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