Subject: [vhdl-200x-dta] RE: White paper on type generics
From: Bailey, Stephen (SBailey@model.com)
Date: Tue Oct 28 2003 - 16:48:16 PST
Peter,
Here's some comments:
1. For subprograms, the proposal introduces a new keyword "parameter" which I believe can be avoided by adjusting the syntax as in:
generic ( generic_list )
procedure designator ( formal_parameter_list );
generic ( generic_list )
[ pure | impure ] function designator ( formal_parameter_list ) return type_mark;
The instantiation syntax can remain unchanged.
I see the major benefit of the parameter keyword in its separation of the generic_list from the formal_parameter_list and not in consistency with entities. Moving the generic list so it precedes the procedure, function, pure/impure keywords provides this lexical separation of the two parenthesized lists.
(NOTE: The functionality provided far out-weighs this relative nit. But, I would like for us to avoid increasing the verbosity of VHDL and introducing new keywords if we can avoid it.)
2. I do not like the requirement that the subprogram body (if separate from the declaration) repeat the generic declaration. I think that this is an unnecessary requirement that increases the verbosity and makes it more difficult to maintain VHDL code as it requires changes in two places. I do not believe it is likely that within the same scope, users would need to define two generic subprograms with the same name and parameter list and to separate subprogram declaration from body.
In fact, in this case, it is very easy to use different names as these subprograms cannot be called directly. Instead, they must be "instantiated" at which time they would be given the identifier by which they are called. At this time, the user instantiating the generic subprograms can give them identical names as long as doing so does not violate the VHDL overloading rules (create an ambiguous homograph).
3. Subprograms as design entities.
As I recall from my Ada programming days, subprograms could be declared at the equivalent of the VHDL design unit level (library units). Being able to do this would enhance the capability provided by generic subprograms. In Ada, generic subprograms could also be instantiated at this level.
This capability for generic subprograms would be far more useful than declaring generic subprograms inside of processes and other subprograms. (I'm not arguing against being able to do that. I'm just pointing out that I see more utility if subprograms could be treated as design/library units.)
-Steve Bailey
> Dear colleages,
>
> Attached is a draft white paper on a proposed extension to
> VHDL for type
> generics. The extension will provide a mechanism for specifying
> type-parameterized data types, such as queues, lists, sets,
> etc. It will
> also allow for type-parameterized design entities.
>
> Looking forward to your comments.
>
> Cheers,
>
> PA
>
> --
> Dr. Peter J. Ashenden peter@ashenden.com.au
> Ashenden Designs Pty. Ltd. www.ashenden.com.au
> PO Box 640 Ph: +61 8 8339 7532
> Stirling, SA 5152 Fax: +61 8 8339 2616
> Australia Mobile: +61 414 70 9106
>
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