1. ASSIGNED PROJECT NUMBER: 1076

2. SPONSOR DATE OF REQUEST: 2004-06-11

3. TYPE OF DOCUMENT: Standard

4. TITLE OF DOCUMENT: IEEE Standard VHDL Language Reference Manual

5. LIFE CYCLE: Full-Use

6. TYPE OF PROJECT: Revision 1076-2002

Modified PAR?
In Ballot? No

7. WORKING GROUP INFORMATION

Name of Working Group: VHDL Analysis and Standardization Group (VASG) a.k.a VHDL-200x Project
Approximate Number of Expected Working Group Members: 30

8. CONTACT INFO FOR WORKING GROUP CHAIR

Name of Working Group Chair: Stephen Bailey
Telephone: 303-775-1655
FAX: 303-652-1578
E-mail: sbailey@model.com

9. CONTACT INFO OF CO-CHAIR/OFFICIAL REPORTER

Name of Co-Chair/Official Reporter: Peter Ashenden
Telephone: +61 8 8339 7532
FAX: +61 8 8339 2616
E-mail: peter@ashenden.com.au

10. CONTACT INFO OF SPONSOR

Sponsor: C/DA
Name of Sponsor Chair: Peter Ashenden
Telephone: +61 8 8339 7532
FAX: +61 8 8339 2616
E-mail: peter@ashenden.com.au

Standards Coordinator (Power Engineering Society Only):
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CO-SPONSOR INFORMATION (THIS IS BEING SPONSORED BY TWO SPONSORS):
Cosponsor:
Name of Cosponsor Chair:
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E-mail:

Standards Coordinator for Cosponsor (Power Engineering Society Only):
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11. TYPE OF SPONSOR BALLOT: Individual

Expected Date of Submission for Initial Sponsor Ballot: 2005-01-31

12. PROJECTED COMPLETION DATE FOR SUBMITTAL TO REVCOM: 2005-06-30

13. SCOPE: This project will revise and enhance the VHDL LRM by including a standard C language interface specification; specifications from previously separate, but related standards 1164, 1076.2 and 1076.3; and general language enhancements in the areas of design and verification of electronic systems.

Completion of this document contingent? No

14. PURPOSE: The VHDL language was defined for use in the design and documentation of electronics systems. It is being revised to incorporate capabilities that will improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, will simplify the maintenance of the specifications.

14a. Reason: General language enhancements improve designer productivity by allowing the specification of models more efficiently or the ability to specify functionality that was previously not possible or impractical to specify in VHDL. Verification capabilities are needed to improve the quality of the designs and to address the significant and growing portion of the electronic system design schedule that is being spent in ensuring the design is functionally correct before manufacturing. These capabilities directly address productivity and quality. Additional capabilities are being added to facilitate standard interfaces for tool interoperability.

15. INTELLECTUAL PROPERTY:

Patent Policy: Yes
Copyrights: Yes   The working group has benefitted from technology donations from EDA companies. These donations have been accompanied by letters of donation with signatures of authorized officials from the donating companies.
Trademarks: No  
Registration of Object: No  

16. SIMILAR SCOPE: Yes

Explanation: P1364 (Verilog): Standard for Verilog Hardware Description Language. There is significant overlap between the capabilities of the two languages. However, both have proven to be accepted in the marketplace with multiple tools supporting one or both languages and with many users that use one or both languages. P1647 Standard for the Functional Verification Language 'e': Some proposed language enhancements in the area of verification will overlap capabilities that may eventually be standardized through this working group. P1800 Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language. This is a proposed effort to extend the capabilities of Verilog. As the market needs better design and verification capabilities, it is natural that both VHDL and Verilog would be working to meet those market requirements for their users.
Sponsor: CS and CAG
Project Number: See above
Project Date:
Project Title:

17. FUTURE ADOPTION - INTERNATIONAL SPONSOR: Yes

Int'l Organization: IEC 93 2
Int'l Contact Person: Alex Zamfirescu
Telephone:
FAX:
E-mail: azro@onebox.com

18. FOCUS ON HEALTH, SAFETY OR ENVIRONMENTAL ISSUES:

Explanation:

19. ADDITIONAL NOTES: Item 9. Peter Ashenden is the document custodian. The WG chair, vice chair and secretary are responsibile for all other duties. Item 13. Previously, part of this work has been conducted under the P1076b PAR. When that work started, only new capabilities were proposed to be added to VHDL in the form of a C language interface for tools. The WG has decided additional enhancements and revision of the standard are required. Therefore, this PAR is being submitted to supersede the P1076b PAR and that work will be subsumed under the broader scope of this PAR.

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