[vhdl-200x] Interface Examples for Thursday's Meeting

From: Jim Lewis <jim@synthworks.com>
Date: Wed Oct 21 2015 - 23:30:25 PDT
Hi All,
On the Interface Top Proposal page, Ernst and I have posted some examples.

In Ernst's examples, he extracted the code from the Complex RTL Signal Based
CPU Bus Interface and SPI Example to explore what the complete code example
would look like.

In my example, I took Ernst's SPI code and put a record signal in the package to
emulate the port interfaces.  It also demonstrates a record whose elements
are being driven by different designs.  Note only the MISO signal is resolved
(std_logic_vector), all other signals in the record are unresolved.   There is a
compile script (Spi.do) that shows the compile order of the example.

I put two other examples that support some of the concepts explored in
Packages as an Interface Construct.   These support the feasibility of a
generic package or something similar being used as a higher level
container for a behavioral interface construct.  Both include compile

Best Regards,

Jim Lewis                                  Jim@SynthWorks.com
VHDL Training Expert                       http://www.SynthWorks.com
IEEE VHDL Working Group Chair
OSVVM, Chief Architect and Cofounder

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Received on Wed Oct 21 23:30:49 2015

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