Re: [vhdl-200x] Heterogeneous Interfaces in VHDL

Following the meetings discussing interfaces and Ernst's excellent white paper 
detailing initial requirements, I've set up some 'whiteboard' pages in order to 
provide a brainstorming mechanism for the group.

If you can't get to the meetings then please add your suggestions, comments and 
questions on these pages. The idea is to keep it free-form bullet points and/or 
examples.

These will be reviewed via the WG meetings.

I've set up three pages initially:

    http://www.eda-twiki.org/cgi-bin/view.cgi/P107/HeterogeneousInterfaceRequirements

This contains the requirements as detailed in Ernst's white paper.
    Ernst, can you update this with the modifications we made at the last
    meeting?



    http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceConcepts

This is some bullet points and examples I put together regarding new mode 
requirements for a simple CPU master/slave interface.



    http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/InterfaceBundles

Some bullet points on the new 'bundle' requirements for interfaces. This is the 
first priority for the next meeting.


These areas can all be accessed from a new 'Whiteboards' link on the main P1076 
web page.

The aim is for the WG meeting to condense these concepts and requirements into a 
final proposal(s).


Regards,

Brent.


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