[vhdl-200x] Modular types

From: Martin.J Thompson <Martin.J.Thompson@trw.com>
Date: Wed Jun 25 2014 - 07:17:30 PDT
Greetings all,

In the last teleconference I was asked to look at what VHDL might be able to implement for "modular types", so I've taken a look at how Ada does it (quotes below are taken from the LRM http://www.ada-auth.org/standards/ada12.html).

Ada defines a modular type from the base integer type (there are "signed integers" and "modular integers").

--- quote
A modular type is an integer type with all arithmetic modulo a specified positive modulus; such a type
corresponds to an unsigned type with wrap-around semantics.
--- endquote

The modulus is known at compile-time.  As you would expect, the range of a modular type is from 0 to modulus-1.

Two extra attributes are defined :

--- quote
S'Mod denotes a function with the following specification:
function S'Mod (Arg : universal_integer)
            return S'Base
This function returns Arg mod S'Modulus, as a value of the type of S.

S'Modulus yields the modulus of the type of S, as a value of the type universal_integer.
--- endquote

The action of operators on modular types is as you might expect:

--- quote
For a modular type, if the result of the execution of a predefined operator (see 4.5) is outside the base
range of the type, the result is reduced modulo the modulus of the type to a value that is within the base
range of the type.
--- endquote

Bitwise "and", "or", "xor" and "not" are all defined for modular types (which is good).  There are interesting implications for the operation of logical operators on modular types which are not modulo-a-power-of-2.  Because they are defined as operating by taking the binary values and operating on them bit-by-bit, if the result is out of range, a final subtraction of the modulus is performed.  This doesn't change the result for powers-of-2, but other moduli may result in non-intuitive (but well-defined) answers!

Ada has limits on the maximum range of a modular type, but I would be tempted to say we shouldn't add one to VHDL, to allow for large bit vectors to be modelled. At the very least I think we should allow for bit vectors of the length of current applications (such as crypto) and add a few bits for expansion.

I would propose that any VHDL implementation of modular types would stick very closely to the Ada definition.

So, are there any features you would like which are not mentioned?  Constraints which do not make sense?


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Received on Wed Jun 25 07:17:46 2014

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