Re: EXTERNAL: Re: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

From: Nick Gasson <>
Date: Fri Mar 28 2014 - 05:44:40 PDT
On 28/03/14 11:31, Evan Lavelle wrote:
> This proposal breaks the clean and abstract nature of VHDL, for no other
> reason than to "reduce the amount of typing". It adds nothing to the
> language that cannot already be expressed relatively concisely. It adds
> confusion for designers, who have a new way to do the same thing, and
> for synthesis vendors, who have to deal with two, potentially
> conflicting, sets of instructions to follow. It adds more potential
> sources of error in the language definition. The new constructs may not
> even be implemented by synthesis vendors; and, if they are implemented,
> users will have to wait years for them.

I couldn't agree more. With this, and the rest of Evan's mail.


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Received on Fri Mar 28 05:44:52 2014

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