[vhdl-200x] Fwd: Bugzilla 286: Incremental binding example is illegal

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---------- Forwarded message ----------
From: Daniel Kho <daniel.kho@tauhop.com>
Date: 14 November 2013 23:58
Subject: Bugzilla 286: Incremental binding example is illegal
To: "vhdl-200x@eda.org" <vhdl-200x@eda.org>


Hi all,
The submitter points us to the incremental binding example in Section 7.3.2.

entity and_gate is
    generic(i1_o, i2_o: delay_length := 4 ns);
    port(i1, i2: in bit; o: out bit);
end entity and_gate;

...

for L2: and_gate use entity work.and_gate(behavior)
        generic map(3 ns, 4 ns)
        port map(i1=>i1, i2=>open, o=>o);

configuration different of half_adder is
...
        for L2: and_gate
            generic map(2.8 ns, 3.25 ns)
            port map(i2=>Tied_High);
        end for;
    end for;
end configuration different;

This example tries to incrementally bind an open input port (i2), yet the
port does not have a default value.

Section 6.5.6.3 states:
"It is an error if a port of mode in is unconnected (see 6.5.6.3) or
unassociated (see 6.5.7.3) unless its declaration includes a default
expression (see 6.5.2)."

This leads me to believe the submitter is correct in suggesting that the
example is illegal (the input port i2 in the configuration specification L2
is left unconnected yet it does not have a default value), but could be
made valid if we specified a default value to the input port:

entity and_gate is
    generic(i1_o, i2_o: delay_length := 4 ns);
    port(i1, i2: in bit := '0'; o: out bit);
end entity and_gate;

Comments?

regards, daniel

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