Hi All, One thing that differentiates VHDL from other languages is the division between protected type declaration and body. In addition within a package, the protected type body must be in the package body. Hence, in the package declarative region the protected type is not yet fully defined. In the current language, I can make the following shared variable declaration and then use it. Should I be able to do this with "deferred" shared variables or should it be illegal? This would mean then that the elaboration of anything that references the shared variable also needs to be deferred. shared variable RV : RandomPType ; signal GlobalInt : integer := RV.RandInt(0, 255); signal GlobalSlv : std_logic_vector(1 downto 1) := RV.RandSlv(0,1,1) ; The reason we need to see use models is that there may be less complicated solutions that acceptably solve the problem. What is the real problem? Having to put the shared variable in a different package or having more than one package reference. One alternate solution could to allow a protected type body (and perhaps a subprogram body) to be included in a package declarative area. This then would make a shared variable use model identical to an architecture. If the problem is having more than one package reference, then don't forget about the VHDL-2008 context clause. Best, Jim > Brief comment from the sidelines by an interested but inactive observer: > > I don't have as much experience in using protected types as I do with other kinds of OO-style programming, so I may be off track here, but... If a package provides some protected type as a service to > the rest of your code, there may well be situations where the same package also should provide some "specimen" instances of that type - maybe as templates that help in the construction of new > instances, maybe as predefined globally accessible objects (I could imagine that being useful, for example, for an objections mechanism). > > It does seem perverse that you can't actually create one of the shared variables inside the package that defines their type. For example, in SystemVerilog I would find it very troublesome if I could > not declare a package-level variable of a class type in the same package that defines the class. > > Jonathan Bromley > > On 18 December 2012 10:32, Martin.J Thompson <Martin.J.Thompson@trw.com <mailto:Martin.J.Thompson@trw.com>> wrote: > > Hi Brent, > > I read your DeferredSharedVariables page yesterday, wasn't aware of the history, so thanks for pointing me to that. > > As with Jim, my use of shared variables is limited to "local" instances, so I haven't come across the problem - I would also appreciate an example of when you find this useful. > > My immediate thought on reading your description was that, rather than introduce a 'deferment', can we not change things so that the "expected" behaviour actually happens? Is there a good reason > for not being able to declare a shared variable in the same region as its type definition? > > Cheers, > Martin > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > believed to be clean. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Dec 18 09:26:05 2012
This archive was generated by hypermail 2.1.8 : Tue Dec 18 2012 - 09:26:42 PST