Re: [vhdl-200x] Records with diectional subtypes

Hi Brent,
So if we allow breaking down ports like that, then perhaps we
need something more - maybe it needs to be a slice and the
slice needs to be unconstrained - and then we would need a way
to specify others being open in a more generic sense.

Perhaps we need an unconstrained/deferred specification such as one
of the following (but not necessarily both):
subtype t_slave is t_cpu_bus port(adr, dat, we, en(<>) : in; sdt, ack, err : out ; en(others) : open );
or:
subtype t_slave is t_cpu_bus port(adr, dat, we, en(array <>) : in; sdt, ack, err : out ; en(others) : open );

Then we could use it as one of the following (but not necessarily both):
t_slave(7 downto 7)
or
t_slave(7)

Jim

> Hi Peter,
> I notice that Jim embedded his comments in the TWiki page. As I know not how
> to do this, nor given my verbosity, do I think that I should be allowed
> to ;-), I will limit myself to Emails.
> My question is embedded below:
> On 16/08/2012 21:07, Jim Lewis wrote:
>> Hi Peter,
>> In the Block Interface proposal, "Candidate: Records with diectional subtypes":
>> http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/BlockInterfaces#Candidate_Records_with_direction
>>
>> Can we extend this to also allow open in the subtype? The following slave does
>> not use the "we" element (perhaps it is read only and never does a write):
>>
>> subtype t_slave is t_cpu_bus port(adr, dat, en : in; sdt, ack, err : out; we : open);
>>
>>
>> Can we allow some ports to not use all elements?
>>
>> type t_cpu_bus is record
>> adr : std_logic_vector(15 downto 0); --Address
>> dat : std_logic_vector(15 downto 0); --Data from master to slave=
>> we : std_logic; --Write enable from master=
>> en : std_logic_(7 downto 0) ; --Enable from master=
>> sdt : std_logic_vector(15 downto 0); --Data from slave to master=
>> ack : std_logic; --Acknowledge from slave=
>> err : std_logic; --Error from slave=
>> end record;
>>
>> subtype t_master is t_cpu_bus port(adr, dat, we, en : out; sdt, ack, err : in);
>>
>> subtype t_slave is t_cpu_bus port(adr, dat, we, en(1) : in; sdt, ack, err : out ; en(7 downto 2), en(0) : open );
> So if I want to instantiate the full 8 slaves (as per your example) would I need 8 separate subtype declarations?
> subtype t_slave0 is t_cpu_bus port(adr, dat, we, en(0) : in; sdt, ack, err : out ; en(7 downto 1) : open );
> subtype t_slave1 is t_cpu_bus port(adr, dat, we, en(1) : in; sdt, ack, err : out ; en(7 downto 2), en(0) : open );
> ...
> subtype t_slave5 is t_cpu_bus port(adr, dat, we, en(5) : in; sdt, ack, err : out ; en(7 downto 6),
> en(4 downto 0) : open );
> ...
> subtype t_slave7 is t_cpu_bus port(adr, dat, we, en(7) : in; sdt, ack, err : out ; en(6 downto 0) : open );
> or have I misunderstood how this is to work?
>>
>> Inside the slave is en seen as en(1) or just en? Is there a notation that allows just en?
>>
>> All questions also on the twiki page.
>>
>> Best,
>> Jim
>
>
> --
>
> Regards,
>
> Brent Hayhoe.
>
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