Re: EXTERNAL: Re: [vhdl-200x] Directional records proposal

If structs (records) and modports were all that were needed, why did SV
bother creating interfaces?

------------
Stephen Bailey
Director of Emerging Technologies, DVT
Mentor Graphics
www.Mentor.com

On 7/13/12 9:17 AM, "Peter Flake" <flake@elda.demon.co.uk> wrote:

>The SV interface does not have directions. The equivalent construct is
>"modport", as was mentioned earlier in this thread.
>
>Since VHDL already has the ability to bundle signals in a record, it does
>not need a new construct for the simplest usage of "interface".
>
>So what is needed is something that is a record with directions and can be
>connected to a record without directions, maybe with subsetting rules.
>
>Peter Flake
>
>-----Original Message-----
>From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
>Of
>Bailey, Stephen
>Sent: 13 July 2012 15:03
>To: vhdl-200x@eda.org
>Subject: Re: EXTERNAL: Re: [vhdl-200x] Directional records proposal
>
>The equivalent construct in SystemVerilog is "interface." Not equivalent
>to
>user-defined modes, but equivalent to the general capability of this
>discussion: bundling all the elements of an interface in a handy package.
> Once you go down this route, it becomes clear that it is more than
>bundling
>of interface elements of different modes. Interfaces have their own
>behavioral (functional) and annotatable characteristics.
>
>------------
>Stephen Bailey
>Director of Emerging Technologies, DVT
>Mentor Graphics
>www.Mentor.com
>
>
>
>
>On 7/13/12 8:56 AM, "Paul Colin Gloster" <Colin_Paul_Gloster@ACM.org>
>wrote:
>
>>On Friday the 13th of July 2012, Jones, Andy D emailed:
>>|----------------------------------------------------------------------
>>|---
>>--|
>>|"VHDL has built in types, but also allows the user to define new types
>> |
>>|and subtypes in terms of built-in types or previously defined types.
>> |
>>|
>> |
>>|VHDL has built-in port modes (in, out, inout, buffer, etc.). [. . .]"
>> |
>>|----------------------------------------------------------------------
>>|---
>>--|
>>
>>Andy,
>>
>>VHDL also allows a user to create a new type (enumeration)
>>independently of already existing types. I was asking for clarification
>>as to whether you wanted to be able to create completely new modes, or
>>whether you wanted what everyone else correctly assumed you meant.
>>
>>|----------------------------------------------------------------------
>>|---
>>--|
>>|"User-defined modes is what I am calling this ability to define new
>> |
>>|composite modes for composite (record) types. [. . .]
>> |
>>|
>> |
>>|Maybe something like "composite modes" is a more appropriate
>>nomenclature? |
>>|
>> |
>>|I'm not married to any nomenclature for this feature; [. . .]"
>> |
>>|----------------------------------------------------------------------
>>|---
>>--|
>>
>>One name is not necessarily better than another.
>>
>>Yours sincerely,
>>Colin Paul
>
>
>
>
Received on Fri Jul 13 12:26:21 2012