RE: [vhdl-200x] Directional records proposal

From: <>
Date: Thu Jul 12 2012 - 10:59:42 PDT


You're on the right track -- this idea has come up before! If you want
more history, you can take a look at the mail and document archives for
the VHDL-200x effort. For a good summary of the current problem
concept, see "Jim's old proposal for interfaces" at

Personally, I think this is a great idea. But I haven't come up with
any good resolution to the points you bring up and the other
"implementation details" you allude to (e.g. those in Jim's proposal).
I would be very happy for you to help this proposal progress by digging
into the detailed issues and proposing solutions.


- Ryan

-----Original Message-----
From: [] On Behalf
Of Olof Kindgren
Sent: Thursday, July 12, 2012 10:34 AM
Subject: [vhdl-200x] Directional records proposal


I recently found this list and the proposed additions to the next VHDL
revision. There seem to be plenty of interesting features, but I'm
missing one feature that irritates me on a daily basis.

VHDL allows us to group signals together with records, but when these
are passed through entity ports, they need to be unidirectional. Many
protocols uses a return-channel - in communication interfaces it can be
some sort of flow-control, and a CPU bus usually has a data/ack/error

This requires me to separate my logical bus into two records (unless I
use inout ports and resolve functions, which is a bit messy)

My proposal is to add an optional directional statement to records to
allow grouping related bidirectional signals

Example with a simple cpu bus:

==Type definition==
type t_cpu_bus is record
   adr : std_logic_vector(15 downto 0); --Address
   dat : std_logic_vector(15 downto 0); --Data from master to slave
   we : std_logic; --Write enable from master
   en : std_logic; --Enable from master
   sdt : rev std_logic_vector(15 downto 0); --Data from slave to master
   ack : rev std_logic; --Acknowledge from slave
   err : rev std_logic; --Error from slave
end record;

==Master entity==
entity master is
   port (
      clk : in std_logic;
      bus : out t_cpu_bus);
end entity;

==Slave entity==
entity slave is
   port (
      clk : in std_logic;
      bus : in t_cpu_bus);

==Top level==
signal cpu_bus : t_cpu_bus;

i_master : master
   port map (
      clk => clk,
      bus => cpu_bus);

i_slave : slave
   port map (
      clk => clk,
      bus => cpu_bus);

Using "rev" for reverse would reverse the direction of the signal
compared to what's defined in the entity port.There should also be a
"bidir" for inout ports.

There are some details that need would need to be worked out for this to
1. This would probably work fine for point-to-point connections, but
what would happen if the bus is connected to more than one in/out pair?
Will the normal resolving rules take care of that?
2. Would it be legal to declare these as inout, or are just in and out
3. Can assignments only be done on individual members of the struct,
i.e. what would happen with cpu_bus := (x"0000", x"0000", '0', '0',
x"0000", '0', '0')?

I'm sure there are other implementation details that I haven't thought
about. but I'm interested in your opinions

Best Regards,
Olof Kindgren

FPGA, ASIC, DSP - embedded SoC design
Received on Thu Jul 12 10:59:45 2012

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