RE: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

Jim,

Good idea. Do you have any feedback on why it was not accepted in 2008? Things we might improve upon?

For the case of multiple request/grant lines (one per endpoint), I would declare all the r/g pairs in the record (using arrays within the bus record), and provide a constant parameter or generic that told the endpoint which pair to actually drive/read while tri-stating or ignoring the others. It's not perfect (requires resolved types), but it gets the job done, and it's not much different than providing an address bus to multiple endpoints, with offsets via generics that tell each endpoint the address range to which it should respond. In most topologies, the record might as well include all of the r/g pairs, since the bus master/arbiter endpoint will have to interact with all of them anyway.

I'm not opposed to including interfaces in classes, but I am concerned about when or if VHDL OO features will ever be synthesizable. If they (OO) are not synthesizable in SV, then it is unlikely they will be in VHDL any earlier. By creating a logical extension to the existing port/mode system, we may be able to entice synthesis vendors to support it more quickly. I can imagine this interface capability (whether OO or not) will only become more important/desirable with increasing usage of IP.

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control
Dallas TX

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
Sent: Tuesday, March 08, 2011 10:35 AM
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

I did a proposal for 2008 revision that did just what Andy suggested below. I post it tonight.

If the intent is to abstract an interface, then records cannot handle a bus with multiple request and grant lines where each slave interface only drives one request and reads one grant. I don't think SV does either.

So while records can solve many problems. I think we need some more sophistication to solve the general case. Since SV interfaces look a little like a class, I was thinking that it would be good to
Integrate interfaces with classes

Best,
Jim
~~~~~~~~~~~~~
Jim Lewis
SynthWorks VHDL Training

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