[vhdl-200x] VHDL enhancements wish list

From: Jakko Verhallen <jakko.verhallen@sitelsemi.com>
Date: Tue Mar 01 2011 - 01:48:27 PST

Hi All,

I also have some small things I ran into:

* conditional bidirectional assignment. e.g. a <=> b when enable='1' else 'Z';
No need to synthesize of course..
* simultaneous starting procedures, like in verilog's fork-join statement.
* package for signed added with clipping. (perhaps I am missing something
existing). The numeric_std just overflows.


Jakko Verhallen
IC Design Engineer
S i T e l Semiconductor BV
Het Zuiderkruis 53
NL-5215 MV 's Hertogenbosch
the Netherlands
tel: +31 73 6408440
fax: +31 73 6408823
e-m: Jakko.Verhallen@SiTelsemi.com
www: http://www.SiTelsemi.com

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Received on Tue Mar 1 01:49:10 2011

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