Re: [vhdl-200x] [Fwd: Re: Time to start up?]

From: Jim Lewis <>
Date: Wed Mar 10 2010 - 13:17:11 PST

Hi Matthias,
I think I will respond to #6.

Cut from previous email:
> 6. Requirement for Delta cycle visibility in simulation
> [Â…] as well as the requirement for the
> simulation tool to make delta cycles visible for making data flow over
> software interfaces visible; [Â…]

Cut from this email:
> Re 6: I am sorry for the cryptic wording, and it’s just an idea of a
> sleepless night (in 2003), probably nothing for the standards committee
> to work on.
> Consider two unsynthesizable components, e.g. as part of a test bench. A
> use case would be a pattern generator driven by the test bench file
> parser module over a bus-like programming interface with address, data,
> ready and so on. To avoid the loss of real time and clock cycles which
> could affect simulation, the two blocks exchange information using delta
> cycles (for a limited number of cycles per time). This data exchange is
> typically not visible in wave windows of, e.g. ModelSim, as display of
> changes is solely time-driven (except if one steps through the processes
> as they are executed). Note that the textual listing of signals and
> related time does make delta cycles transparent, but uses a rather
> different UI, to say the least.

What you are asking for is a tool feature and not a language feature.
A vendor is permitted to show you delta cycles if they wish in the wave
window. Some provide you with this type of capability in an
alternate window. I will provide more details off reflector.

BTW, I also use delta cycle handshaking for my testbench models.
I do not find debugging something like this something I need to do
on a regular basis since I have put the handshaking into a group
of procedures and I call the appropriate procedure to do the handshaking
for each model.


Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Wed Mar 10 13:17:42 2010

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