[vhdl-200x] Next VHDL-200x Meeting

Subject: [vhdl-200x] Next VHDL-200x Meeting
From: Bailey, Stephen (SBailey@model.com)
Date: Wed Feb 04 2004 - 13:31:47 PST

Date: Thursday, 4 March 2004
Time: 08:30 - 17:00
Place: Mentor Graphics, Conference room B2.105 (Tasmania, 2nd floor above reception area)
           Mentor Graphics Silicon Valley Headquarters
          1001 Ridder Park Drive
           San Jose, CA 95131


- VHPI Status (Peter Ashenden and/or Francoise Martinolle)
  - Report on LRM editing work

- Review fast-track status (Jim Lewis)
  - Proposals completed (or nearly so)
  - Proposals remaining

- ISAC Status (John Willis)
  - IRs to be resolved for next revision and their status

- PSL incorporation status (Steve Bailey)
  - Current PSL status
  - What VHDL changes/accomodations are being proposed

- Encryption/protection proposal (Deepak Pant)

Please see www.eda.org/vhdl-200x for published language change proposals (primarily under fast-track).

Minutes from the Dec meeting.

  Deepak offered to investigate the use of the encryption/protection mechanism that Cadence has proposed for 1364 with VHDL-200x.

  Several fast-track issues were discussed and promising resolutions to them identified. These will be incorporated into language change proposals and published (some already have been). John Ries, Peter Ashenden and Jim Lewis provided significant inspiration here.

  Peter Ashenden and John Willis discussed object-oriented extensions to VHDL (SUAVE from Peter and VHDL-X from John). We determined that the highest priority issues for the next revision are in the area of generalized generic parameterization (generic types, subprograms, etc.). With more powerful generic capabilities, Bhasker would be able to build several of his proposals on general language features and not hard-code them into VHDL. Bhasker participated in this portion of the meeting via telecon. Once Peter finishes the VHPI LRM editing work, he will focus on the enhanced generics capabilities.

  We did not have sufficient time to discuss PSL/VHDL integration issues beyond an issue or two discussed within the fast-track portion of the meeting. Steve did provide an update on PSL and SystemVerilog Assertions harmonization efforts: The same symbol/keyword in both have the same meaning, general semantic alignment and some additional syntactic alignment. But, PSL and SVA are on track to remain separate languages. The PSL 1.1 LRM will incorporate the results of the harmonization and potentially other enhancements to PSL as well.

Stephen Bailey
TME, Mentor Graphic's Model Technology Group
303-775-1655 (mobile, preferred)
720-494-1202 (office)

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