RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g


Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Scott Thibault (thibault@gmvhdl.com)
Date: Fri Dec 26 2003 - 07:22:30 PST


> I agree; this seems to me to be a significant weakness of 1076.6. I've
> written code that uses booleans, and I do it the same way as I imagine
> everyone else does it: you have a physical level outside the chip, you
> set the boolean equivalent at the top level of the chip (possibly
> inverting the external signal in the process), and you then use the
> boolean signal internally.
>
> The only justification I can see for 1076.6 to define '1' as true and
> '0' is false is to have a default for users who have forgotten to set
> their physical signal levels. Surely it would be equally (or more) valid
> for the tool just to give a warning in this case? In any event, this
> can't be used a justification for locking VHDL into a 'positive logic'
> mindset.

I agree. To take full advantage of the type system, there could be two
separate types for active high vs. active low signals. Active high signals
could then map '1' to true, and active low signals can map '0' to true. As
an added benefit, the type system would catch component instantiation errors
that associate active high signals to active low ports and vise versa.

--Scott Thibault
Green Mountain
Computing Systems, Inc.
http://www.gmvhdl.com



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