RE: [vhdl-200x] Call for Advisory Vote: Simple Subset of PSL

Subject: RE: [vhdl-200x] Call for Advisory Vote: Simple Subset of PSL
From: Jayaram Bhasker (
Date: Thu Sep 11 2003 - 08:59:37 PDT


I vote YES to the proposal. Furthermore I would like to see PSL incorporated as
native VHDL constructs rather than as pragmas.

- bhasker

J. Bhasker, eSilicon Corp
1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104, 610.439.6831, 610.770.9634(fax)

-----Original Message-----
From: Bailey, Stephen []
Sent: Wednesday, September 10, 2003 3:48 PM
To: ''
Subject: [vhdl-200x] Call for Advisory Vote: Simple Subset of PSL

The assertions team has decided to pursue the incorporation and integration of the simple subset of PSL as the best way to enhance the assert statement into a broader assertion-based verification capability. The simple subset limits the properties that can be expressed to only those in which time moves monotonically forward (which is the only way simulators know how to deal with time).

Because we do not yet have a detailed proposal on the specifics of the PSL incorporation and integration, this Call for Vote is NOT a final CfV. Instead, it is best viewed as an advisory vote; the purpose of which is to provide some assurance to the assertions team that they won't be wasting their time in pursuing PSL as the basis for the detailed proposal. (By assurance, I mean that we won't later find out that a majority or very significant minority would never vote to approve the detailed proposal due solely to the fact that the proposal is based on PSL.)

Also, from a practical perspective, I am in the process of submitting 3 different papers for possible publication and presentation at conferences and EE Times. These papers will all reference the fact that PSL has been chosen as the basis for VHDL's ABV capabilities. While I don't anticipate a negative response to this advisory vote, I would rather have the vote than be made a fool (and waste alot of people's time over the next several months)!

As the papers are in process of review and this is an advisory vote, I require a quick turnaround on this vote:

  Friday, 12 Sep 03, 0900 EDT.

The question to be voted on:

   Should the assertions team continue constructing a detailed language change proposal based on incorporating and integrating PSL into VHDL?

Yes replies require no comments. However, I request any no responses to provide rationale for the no comment. Replies can be sent to me ( or to the email reflector (

DASC WG voting rules apply. You must be a DASC member. To confirm your membership in DASC, see The DASC home page has a link to the membership application.

Thank you for your prompt consideration.

Stephen Bailey
TME, Mentor Graphic's Model Technology Group
303-775-1655 (mobile, preferred)
720-494-1202 (office)

This archive was generated by hypermail 2b28 : Thu Sep 11 2003 - 09:01:47 PDT