Subject: RE: [vhdl-200x] CFA: Priorities
From: Erich Marschner (email@example.com)
Date: Wed Mar 12 2003 - 07:00:59 PST
The evaluation performed by the FVTC took more than a year to complete. It would be difficult to summarize completely the reasons behind the selection of Sugar 2.0 over the other donated languages (Temporal e, CBV, and ForSpec). Suffice to say that the FVTC went through a very careful and detailed process that involved collecting example properties, developing requirements, analyzing donated languages w.r.t. requirements, and successive balloting to reduce the four candidates down to two (Sugar and CBV). The two finalist languages were then extended by their respective design teams in order to fully address the FVTC requirements, and then the FVTC held a final ballot in which Sugar 2.0 was selected as the basis for the standard. It should be noted that the creation of the PSL LRM from the Sugar 2.0 definition involved a significant number of the FVTC participants, including the temporal logic experts who were responsible for the CBV and Temporal e donations, so the final language reflects not only consen
sus among the FVTC participants, including language donors, but also has benefited from wide review.
You can read the entire history, if you'd like, in the email archive at http://www.eda-twiki.org/vfv/hm.
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: firstname.lastname@example.org
Vmail: +1 410 872 4369 Email: email@example.com
| -----Original Message-----
| From: Evan Lavelle [mailto:firstname.lastname@example.org]
| Sent: Tuesday, March 11, 2003 12:43 PM
| To: VHDL-200x
| Subject: Re: [vhdl-200x] CFA: Priorities
| Rob Anderson wrote:
| > I agree with proceeding on the plan to add Sugar.
| > We seem to have a question about how much work it will be, however
| > we have a commitment from Erich to do much of the work.
| > I think the first steps should be to set up a reflector, and a
| > web space to put information, docs, pointers for sugar as it is
| > being considered for VHDL. I trust Erich that this specification
| > is useable, but it is necessary to promote what we are doing.
| Could I also ask that you post the docs giving Accellera's
| reasons for
| selecting Sugar as a base, rather than the competition.
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