Subject: RE: [vhdl-200x], vital issues
From: Peter Ashenden (peter@ashenden.com.au)
Date: Fri Mar 07 2003 - 08:06:38 PST
Bhasker,
> With two of the simulators that I use, as long as the verilog
> models are compiled into work,
> I have no problem linking them in. So the question is, can I
> compile verilog models into a
> vhdl library called VLIB and use "use VLIB.all;" to link the
> models during elaboration? Jim, I guess
> this is what you are looking for, right?
This initially made me think of foreign architectures. The difference,
however, is that you don't want to have to write a VHDL entity
declaration corresponding to the Verilog module. Instead, you want VHDL
to be able to understand the Verilog module's interface. That would
mean defining a correspondence between Verilog port names, types and
directions on the one hand and VHDL port nameds, types and directions on
the other hand. Am I understanding this correctly?
Cheers,
PA
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106
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