Dmitry Korchemny Dmitry Korchemny 2015-12-14T16:55:04Z 14.00 9375 9705 270 615 False False ID Project Reporter Assigned To Priority Severity Reproducibility Product Version Category Date Submitted View Status Updated Summary Status Resolution Fixed in Version 5510 SystemVerilog P1800 Dmitry Korchemny normal text always SV-AC 2015-12-13 public 2015-12-14 Definition of sequential property is awkward new open 5248 SystemVerilog P1800 Françoise Martinolle normal minor always 1800-2012 SV-AC 2015-03-21 public 2015-03-24 Clarify the meaning of "function shall be automatic "in section 17.8 and 16.6 new open 5231 SystemVerilog P1800 Dmitry Korchemny normal major always 1800-2012 SV-AC 2015-03-04 public 2015-03-05 Assertion system tasks are not well-defined for assertions in packages new open 5194 SystemVerilog P1800 Daniel Mlynek normal text always 1800-2012 SV-AC 2015-02-05 public 2015-02-05 $inferred_clock description should mention checkers and allowed types for $inferred_clock new open 4173 SystemVerilog P1800 Ben Cohen normal minor always P1800-2012/D5 SV-AC 2012-05-23 public 2014-11-27 16.12, 17.3 clarify that range is bounded by constant expression new open 4991 SystemVerilog P1800 Erik_Seligman normal text always 1800-2012 SV-AC 2014-08-08 public 2014-08-08 Need to clarify that clock flow into sampled value functions works just like other sequence ops new open 4201 SystemVerilog P1800 Dana Fisman normal minor always SV-AC 2012-06-26 public 2014-06-27 Missing info with regard to untyped formal arguments new open 4037 SystemVerilog P1800 Ben Cohen urgent minor always P1800-2012/D4 SV-AC 2012-02-09 public 2012-02-13 Define false vacuity and contributions to pass/fail counters in simulation new open 2248 SystemVerilog P1800 Neil Korpusik Scott Little normal minor always P1800-2008/D4 SV-AC 2008-01-25 public 2011-12-14 "leading clock" - Champions feedback - items related to Mantis item 1683 assigned open 3928 SystemVerilog P1800 Erik_Seligman normal minor always P1800-2012/D3 SV-AC 2011-11-16 public 2011-11-16 Fix text in LRM encouraging incorrect coding of "clk iff enable" new open 3924 SystemVerilog P1800 Erik_Seligman normal minor always P1800-2012/D3 SV-AC 2011-11-14 public 2011-11-14 Need to clarify behavior when sequence event used as property clocking new open 3672 SystemVerilog P1800 Ed Cerny normal major always P1800-2012/D1 SV-AC 2011-07-13 public 2011-07-13 hierarchical access to named block in assertion action blocks new open 3552 SystemVerilog P1800 Ben Cohen normal minor always P1800-2012/D1 SV-AC 2011-05-10 public 2011-06-21 16.14.6 Sequence methods // .triggered need further clarification new open 3614 SystemVerilog P1800 Dmitry Korchemny Dmitry Korchemny normal minor always SV-AC 2011-06-15 public 2011-06-15 Free variable randomization with assumptions with various clock domains assigned open 3059 SystemVerilog P1800 John Havlicek Scott Little normal minor always 1800-2009 SV-AC 2010-04-27 public 2011-03-04 Study PSL local variables and determine if any alignment is warranted. assigned open 2947 SystemVerilog P1800 user199 user199 normal major always 1800-2009 SV-AC 2010-01-19 public 2011-03-04 Module variables from within function or task not sampled, LRM and practice contradictory assigned open 2891 SystemVerilog P1800 user199 user199 normal minor always P1800-2009/D9 Recirc SV-AC 2009-09-24 public 2011-03-04 17.3.1 Clarification on procedural concurrent assertions upon instantiation of checker assigned open 2810 SystemVerilog P1800 user199 user199 normal minor always P1800-2009/D9 Recirc SV-AC 2009-07-15 public 2011-03-04 Checker instantiation in an always or initial procedure assigned open 2752 SystemVerilog P1800 user199 user199 normal minor always P1800-2009/D8 Ballot SV-AC 2009-05-25 public 2011-03-04 P1800-2009 Checker: Clarification on use of automatic variables in "blocks" assigned open 2560 SystemVerilog P1800 Dmitry Korchemny user199 normal text always P1800-2009/D8 Ballot SV-AC 2009-01-08 public 2011-03-04 Inconsistent description of conditional property operators assigned open 2555 SystemVerilog P1800 John Havlicek Scott Little normal minor always P1800-2009/D8 Ballot SV-AC 2009-01-05 public 2011-03-04 Clarify relationships of different local variable binding mechanisms assigned open 2546 SystemVerilog P1800 Shalom Bresticker Scott Little normal minor always P1800-2009/D8 Ballot SV-AC 2008-12-28 public 2011-03-04 'empty match' and 'vacuous success' are not clearly defined in LRM assigned open 2367 SystemVerilog P1800 Jonathan Bromley Dmitry Korchemny normal text always P1800-2008/D4 SV-AC 2008-04-23 public 2011-03-04 Clarification: sampled-value functions are unaffected by disable-iff assigned open 2858 SystemVerilog P1800 user199 normal major always P1800-2009/D9 Recirc SV-AC 2009-08-24 public 2010-04-27 Clarify the rules for assigning a value to a non-checker variable from within a checker new open False False