VHDL Issue Number: IR.07.01 Classification: Language Definition Problem Language Version: VHDL-1076.1-2007 Summary: Explicitly declared terminals and quantities not defined in LRM Related Issues: Bug 188 in P1076 bugzilla, which was lost Relevant LRM Sections: 4.3.1.5, 4.3.1.6 Key Words and Phrases: explicitly declared objects Current Status: Submitted 1076.1-2007 Disposition: Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No ISAC Issues) Superseded (ISAC Issues Outstanding) Disposition Rationale: Superseded By: N/A ----------------------- Date Submitted: Jan 15, 2014. bugzilla 188: January 8, 2008 Author of Submission: Ernst Christen Author's Affiliation: Mentor Graphics Corporation Author's Post Address: 8005 SW Boeckman Rd, Wilsonville, OR 97070 Author's Phone Number: 503-685-0759 Author's Fax Number: Author's Net Address: christen.1858@comcast.net ----------------------- Date Analyzed: Author of Analysis: Revision Number: 1 Date Last Revised: Description of Problem ---------------------- Subclause 5.4 requires each quantity in the quantity list of a step limit specification to be an explicitly declared quantity or a member of such a quantity. The term "explicitly declared quantity" is not defined in the LRM, neither is the term "explicitly declared terminal. Proposed Resolution ------------------- Add a definition of an explicitly declared terminal to subclause 4.3.1.5. Add a definition of an explicitly declared quantity to subclause 4.3.1.6. 1076.1-ISAC Analysis & Rationale -------------------------------- 1076.1-ISAC Recommendation for IEEE Std 1076.1-2007 --------------------------------------------------- 1076.1-ISAC Recommendation for Future Revisions -----------------------------------------------