Champions:
Karen Pieper
Shalom Bresticker
Surrendra Dudani
Stu Sutherland
Bassam Tabarra
Francoise Martinole
Dave Rich
Guests:
Steve Dovich
Patent Policy
The chair directed everyone's attention to
http://www.verilog.com/IEEEVerilog.html where a link to
the IEEE
policy was reviewed.
Dates:
01/05/05: P1800 Conference call 8:00 am
Week before
Action Item:
Stu requests that the approved method for creating a large proposal also include the frame or word source for the proposal in the files attached to the issue. Karen to update the operating procedures and send mail to all the committees.
Issue Discussion
50: We recommend that this proposal be approved. Unanimous. 342 has already been incorporated as a separate proposal.
275: Proposal to approve with the comment that the editor needs to work with the author on some minor editorial issues (Shalom’s mail:
Comments:
1. On
bottom of page 2, top of page 3:
bit
[11:0] b = 12'ha41 ;
string
s2 = string' (b) ; // sets s2 to 'h0a41
I believe the 2nd line should be
string
s2 = string' (b) ; // sets s2 to 16'h0a41
as
'h0a41 is 32 bits.
2. On
bottom of page 3:
r =
{"H",""}; // yields "H\0" => "" is converted
to 8b0
b =
{"H",""}; // yields "H" => "" is the
empty string
a[0] =
"h"; // OK same as a[0] = "cough" ;
The symbol "=>" is
not appropriate here.
That symbol means
"implies", which is not the case here.
A simple period would be enough.
In the 3rd line above, there
should be a period or a comma between "OK" and
"same
as".
Also, in all the examples, not
just those quoted here, all quotation marks
should
be straight up and down.
3. In Table 3-2 (top of page 4):
"If both operands are
string literals, the expression is the same Verilog
equality
operator for integer types."
Besides being incorrect (an
expression is not an operator), it is not clear what
the
intended meaning is.
4. Same place: 'The special
value " " is allowed.'
Was this supposed to be the
empty string? There is a space here between the two
quotation
marks,
so it
is not the empty string.
5. Page 4, "Replace Section
3.7.7" should be "Replace Section 3.7.2".
6. 3.7.2, page 4 bottom:
"If the second argument to putc is zero, the string is unaffected: if c is zero,
then str is unchanged."
The second part of the sentence
is redundant.
7. Page 5:
The first "Replace Section
3.76" should refer to 3.7.6, the second to 3.7.7.
Shalom
). Opposed: Dave (it is not functionally backward compatible, and may cause problems with existing usage of strings in Verilog. Passing Verilog strings to SV may cause unexpected truncation). Everyone else votes yes.
334, 197, 203, 271: Return to SV-EC for resolution as duplicate of 275. Unanimous.
314: Encryption: Draft in circulation with an email vote
open. There are a couple of observations
of some typos and a recognition that we didn’t include
comma separation of pragma expressions. The meeting is at
The Champions feel that that they have not had an opportunity to review the remainder of the proposal and as a result cannot make a recommendation at this time. If this proposal is only approved in the 26th meeting, then there is risk that it will not make it into the ballot draft. The Champions feel that this proposal should not be rushed just to make a deadline.