Hi, Stu.
Not quite.
First of all, for your reference, the Mantis and proposal were filed against the electronically-published version of IEEE Std 1800-2009. Before writing the proposal, I downloaded the current version from the IEEE web site and used it as my reference.
Now, I have P1800-2012/D2 and yes, most of the problems are already solved, but a few are not.
The problems that remain:
The very first change in the proposal makes this change to 35.4:
The same global subroutine can be referred to in multiple import declarations in different scopes or/and with
different SystemVerilog names (see <ADD HYPERLINK>35.5.4).
When I go to Draft 2 (page 902 of the PDF, numbered as page 866 at the bottom), I find that "35.5.4" appears in underlined blue, but it is not a hyperlink. Clicking on it does nothing.
The next hyperlink is also not OK.
The last change in the proposal is also not yet fixed. H.13.1 has a link to 35.5.4 that still does not work.
Regards,
Shalom
3272<http://www.eda-twiki.org/svdb/view.php?id=3272> SV-CC two cross-references are not hyperlinked
There is a proposal (3 pages).
This is the first time this proposal has gone to the Champion's.
On May-11-2011, the SV-CC PASSED this proposal (unanimous)
Approve __ Oppose _X_
Stu: None of the problems listed in this proposal exist in P1800-2012/D2. I checked every hyperlink listed in the proposal and they match what the proposal wants things changed to, and all the hyperlinks work. The proposal does not say what version of the standard it was written against, but the problems no longer exist. Recommend this be returned to the CC committee to be verified against P1800-2012/D2 and closed as no changes needed.
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