RE: [sv-champions] Email vote ending June 11, 2011

I filed this issue as Mantis 3607.

Shalom

> -----Original Message-----
> From: owner-sv-champions@eda.org [mailto:owner-sv-champions@eda.org] On
> Behalf Of Bresticker, Shalom
> Sent: Sunday, June 12, 2011 7:38 AM
> To: sv-champions@eda.org
> Subject: RE: [sv-champions] Email vote ending June 11, 2011
>
> Hi, Francoise.
>
> Regarding Mantis 2889,
>
> SV-BC discussed the issue of determining port kind for an explicitly named
> port, and decided to separate this issue from 2889. There is an action item
> in the SV-BC agenda/minutes:
>
> 12/06/10 Matt open new Mantis item covering determination of port kind
> for .named_port connection (23.2.2.3).
>
> 2889 does not touch this issue, but neither does the current LRM. 2889 does
> not change the current situation for the worse.
>
> Regards,
> Shalom
>
>
> > > 35. 2889 <http://www.eda-twiki.org/svdb/view.php?id=2889> Errata SV-BC minor
> > > .named_port(expression) in ANSI-style port declaration list should
> > > reset properties
> > > There is a proposal - adds a few new paragraphs
> > > On January 28, 2011 the SV-BC concluded an email vote that
> > > unanimously approved the attached proposal.
> > >
> > > Approve __ Oppose _X_
> >
> > I think that the proposal is incomplete, it does not say how to determine
> if
> > a named port expression is a wire or a variable.
> > Specifically in the example:
> > module mh22 (input wire integer p_a, .p_b(s_b), p_c); What is the port
> p_b?
> > a wire or a variable? The rules for port declarations determine the port
> > kind of by looking at the datatype of the port. Do these rules apply?
> > Either we apply the rules for normal port declarations or we have to
> choose
> > a default for non explicit port kind. For example the default is variable.
> > If we have to follow the normal port declaration rules, since p_b has no
> > explicit port kind and this is NOT the first port, we need to apply the
> > following rules:
> > "
> > If the port kind is omitted:
> > - For input and inout ports, the port shall default to a net of default
> net
> > type. The default net type can be changed using the `default_nettype
> > compiler directive (see 22.8).
> > - For output ports, the default port kind depends on how the data type is
> > specified:
> > - If the data type is omitted or declared with the implicit_data_type
> > syntax, the port kind shall default to a net of default net type.
> > - If the data type is declared with the explicit data_type syntax, the
> port
> > kind shall default to variable.
> > - A ref port is always a variable.
> > "
> > Since p_b inheritis the input direction, first bullet applied and this is
> a
> > net.
> >
> > But what about if the port p_b was the first port, which rules do we apply
> > to determine the port kind, direction and data type?
> > module mh22 (.p_b(s_b), p_c);
> > Do we expect the rule to apply: (i.e this is not a ANSI style port)
> > For the first port in the port list:
> > - If the direction, port kind, and data type are all omitted, then the
> port
> > shall be assumed to be a
> > member of a non-ANSI style list_of_ports, and port direction and type
> > declarations shall be declared
> > after the port list.
> > I think I would like this to be specified with more details.
>
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> Intel Israel (74) Limited
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