If you already mentioned const casting: > What I thought when reading the proposal is that the constant > casts give a way to capture a current value from the > procedural context and pass it into the checker. This might > be a value of a loop iterator. 2398 describes const casting in this way: "Procedural concurrent assertions shall also use the sampled values of their arguments, with the following exception: a procedural concurrent assertion shall not sample any const expression or automatic variable, but shall instead save the value of the expression or variable at the time the assertion evaluation attempt is added to the procedural assertion queue. Using a const cast for expressions involving non-automatic variables provides a mechanism for avoiding sampling semantics for that variable." I'm not very happy about using "const" to describe those semantics. It seems a very non-intuitive and confusing use of the term "const", as a loop iterator, for example, is any BUT constant. After years of having to explain to Verilog students that "reg" does not mean "register", now we will have to explain that "const" does not always really mean "constant"?? Regards, Shalom --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Aug 13 01:37:10 2008
This archive was generated by hypermail 2.1.8 : Wed Aug 13 2008 - 01:37:14 PDT