RE: [sv-champions] 5-day email vote - 1556

>     http://www.eda-stds.org/svdb/view.php?id=1556
> 
>         2)  Doesn't this break backward compatibility with traditional
> Verilog by requiring an explicit lifetime keyword for all initialized
> variables in static tasks and functions?
[DR] No, because traditional Verilog only let you initialize variables
at the module level, most likely to avoid the problem here.
> 
>         3)  In any case, reverting this change is not necessary.
Users
> are free to add 'static', and methodologies are free to require
> 'static', but there's no language reason to again make it mandatory
for
> everybody.
[DR] This falls into the category of restrictions for the benefit of the
user, like not allowing 'tri reg' or requiring extra parenthesis around
assignments in expressions. The probability of the user making a mistake
AND the difficulty in debugging the problem so great that the committee
felt it was justified.
> 
>         4)  The example is confusing.
[DR] Not to me :)
> 
>         5)  The comments in the example are wrong, because they say 1
2
> 3 3 3 3 3 3 3 3 should be printed, but actually it should be 2 3 4 4 4
4
> 4 4 4
[DR] The results assumes the illegal statement is not executed. Perhaps
that should be shown as a completely separate module. Would that be less
confusing?
> 
> 

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