RE: [sv-champions] SystemVerilog Champions meeting - April 17th

Hi,

> Mantis 890
>    SV-890-9-amended-part1.pdf
>    SV-890-7-part2.pdf

I'm looking at this proposal really for the first time and I did not
have time to study the entire thing. But I found some small issues:

For example, the very first change substitutes the following text:
"The signal_identifier specifies a signal (a net or variable) in the
scope enclosing the clocking block declaration, and declares a clockvar
in the clocking block."

What is a clockvar? Clockvars are not described till 15.14, where it
says, "The clockvar_expression is either a bit-select, slice, or the
entire clocking block output whose corresponding signal is to be
driven". The use here of the term without explanation is confusing.

--

"The timing used to drive and sample all other signals specified in a
given clocking block is governed by its clocking event. See 15.12 and
15.14 for details on the precise timing semantics of sampling and
driving clocking signals."

All three uses of 'clocking' here are bolded. Why? I think only the
first represents the 'clocking' keyword.

--

In 15.10:

"Cycle delay timing controls shall not be legal for use in
intra-assignment delays either in blocking or nonblocking assignment
statements." - change "either in" to "in either".

-- 

In 15.12:

"NOTE - When the clocking block event is triggered by the execution of a
program, there is a potential race between the update of a clocking
block input value and programs that read that value without
synchronizing with the corresponding clocking event. This race does not
exist when the clocking block event is triggered from within a module."

This note is the only place where "clocking block event" is used. Is
this the same as "clocking event"? Or is it "the event associated with
the clocking block name"?

"When an input or inout clockvar appears in any expression its value is
the signal's sampled value. That is, the value that the clocking block
sampled at the most recent clocking event."

Here again, the second 'clocking' is bold, and probably should not be.

"When the same signal is an input to multiple clocking blocks, the
semantics is straightforward"

This is not a change proposed by the proposal, but I just noticed that
"semantics is" should be "semantics are".

-- 

In 15.14:

"The driver so created shall have (strong1, strong0) drive strength and
shall be updated as if by a continuous assignment from a variable inside
the clocking block."

strong1 and strong0 are keywords, and so should be bold.

"The created driver shall be initialized to 'bZ"

This is very picky, but for consistency, it probably should be "'z".


Shalom

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