Clause 18.15, the bind statement

PROPOSAL

In clause18.15, ADD  the following blue text in the indicated position:

 

In this example, interface range is instantiated in the module cr_unit. Effectively, every instance of module

cr_unit shall contain the interface instance r1.

 

The bind_instantiation portion of the bind statement allows the complete range of SystemVerilog instantiation

syntax. This means that both parameter and port associations may appear in the bind_instantiation. All actual

ports and parameters in the bind_instantiation refer to objects from the viewpoint of the bind_target instance.

 

When an instance is bound into a target scope, the effect will be as if the instance was present at the very end
of the target scope.  That means all declarations present in the target scope are visible to the bound instance.

 

If multiple bind statements are present in a given scope, the order of those statements is not important.

An implementation is free to elaborate bind statements in any order it chooses.

 

The following is an example of a module containing a bind statement with complex instantiation syntax. All

identifiers in the bind instantiation are referenced from the bind_target’s point of view in the overall design hierarchy.