RE: Email Ballot due Monday June 18th

OK, not the 2nd page of PDF, "ii", but the 38th page of PDF, "2".

Got it now.

-- Brad

-----Original Message-----
From: Kaiming Ho [mailto:kaiming.ho@iis.fraunhofer.de]
Sent: Sunday, June 17, 2012 11:53 PM
To: Maidment, Matthew R
Cc: Brad Pierce; sv-xc@eda.org
Subject: Re: Email Ballot due Monday June 18th

Hello Brad, Matt:
   My intention when I filed the mantis was not to suggest that the
abstract on page (ii) needs changing. In fact, I think that the
text in P1800/D5:

   Abstract: This standard provides the definition of the language syntax
   and semantics for SystemVerilog, which is a unified hardware
   design, specification, and verification language. The standard
   includes support for modeling hardware at the behavioral, register
   transfer level (RTL), and gate-level abstraction levels, and for
   writing testbenches using coverage, assertions, object-oriented
   programming, and constrained random verification. The standard also
   provides application programming interfaces to foreign programming
   languages.

is perfectly fine. The one in P1800/D4, which is referenced in the
change is not, but I don't think that can serve as a basis.

My intention was that:
   - on p2, section 1.4, the incorrect definition of "SystemVerilog"
     be removed, and similarly
   - on p1299 (Annex P).

regards,
kaiming

On 17.06.2012 5:50 PM, Maidment, Matthew R wrote:
> That covers my feedback. Thanks, Brad!
>
> On Jun 16, 2012, at 11:56, "Brad Pierce"<Brad.Pierce@synopsys.com<mailto:Brad.Pierce@synopsys.com>> wrote:
>
> Hi Matt and Kaiming,
>
> Uploaded revised proposal for Abstract.
>
> http://www.eda-twiki.org/svdb/view.php?id=4146
>
> -- Brad
>
>
> <4146_abstract_2.pdf>

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